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SPI Controller

This External SPI IP basically has the same behavior like 8051's internal SPI controller. The IP provides the interface to EMIF (External Memory Interface) of 8051 core in CME FPGA and can be programmed to work as master or as slave device.


  • Full duplex mode
  • Three wire synchronous transfers
  • Master or Slave mode
  • Seven SPI Master baud rates
  • Slave Clock Master baud rates
  • Serial clock with programmable polarity and phase
  • Data transmitted Most Significant Bit(MSB) first and Least Significant Bit(LSB) last
  • Slave select Output port to control external slave devices
  • Programmable address space for internal registers
  • Support 8 bits,16bits,32bits SPI data width
  • Support AHB interface and EMIF interface
  • Programmable BASE_ADDR for internal registers, EMIF interface base address must be 0x20 aligned,
  • AHB interface address must be 0x80 aligned
  • Support AHB single no-sequence transaction