HME - P3P100-Products Center

FPGA
6-input Look-up Tables High Performance FPGA Fabric		112K logic cells 139,200 register elements
Embedded Memory Block		180 360Kb programmable true-dual-port EMB block, totaling 6480Kb LRAM with a total capacity of 368Kb
Embedded DSPs block		180 DSP (MAC) blocks, 3518 or 360 DSP（MAC) blocks, 1818 or 720 DSP (MAC) blocks, 189 or 1440 DSP（MAC）blocks, 1010
Clock Network		32 de-skew global clocks Flexible hierarchical clock network 1 OSC 13 PLLs Dynamic clock management in system
I/O		Support the following single-ended standards: 3.3/2.5/1.8/1.5/1.2V LVTTL/LVCMOS 1.8/1.5/1.35/1.2V SSTL/HSTL Support the following differential standards: LVDS RX/TX, BLVDS, LVPECL Support for on-chip termination resistors Support for MIPI D-PHY level standard Up to 1.4Gb/s per LVDS I/O Supports IDDR2/ODDR2 input/output modes Supports serial-to-parallel and parallel-to-serial conversion functions
Hard DDR		Supports DDR3/3L/4 and LPDDR3/4/4X combo PHY Hard DDR3/3L/4 and LPDDR3/4/4X controller
MCU
ARM Cortex-M3 MCU	High performance 32-bit processor, frequency up to 200MHz Outstanding processing performance combined with fast interrupt handling Enhanced system debug with extensive breakpoint and trace capabilities Efficient processor core, system, and memories Single cycle multiplication, hardware divide Integrated sleep mode
Peripheral	8 Timers 1 Watch Dog Timer 3 I2C interfaces 3 SPI interfaces 1 QSPI interface 3 UART interfaces 1 GPIO, 32-bit 1 4-channel DMA
Memory
Embedded SRAM Block	2 SRAMs, 4K*32b, total 32KB
Configuration
Configuration Mode JTAG Mode AS Mode PS Mode	In System Configuration
Security
256-bit eFuse 128-bit AES encrypted data stream Protects user FPGA data streams and MCU firmware
Package
PBGA676 TFBGA324

Part Number		P3P100-M0H1
Programmable Logic Block (PLB)	Logic cells (K)	112
	LUT6	69,600
	Register	139,200
Embedded Memory Block (EMB)	36Kb	180
	18Kb	360
	9Kb	720
	Max (Kb)⁽¹⁾	6,480
DSP⁽²⁾	35b*18b⁽³⁾	180
	18b*18b	360
	18b*9b	720
	10b*10b	1440
GCLK_TILE⁽⁴⁾		13
OSC		1
PVTS		4
DDR3/3L/4 and LPDDR3/4/4X⁽⁵⁾		1
MCU	Cortex-M3	1
	UART	3
	I2C	3
	SPI	3
	GPIO	64
	Timer	8
	WDG	1
	DMA	1
SRAM	4K*32b	4
SRAM	Total (KB)	64
eFuse	256b	1
Package (unit: mm)		Max User IO (HRIO/HPIO)
PBGA676 (27.00×27.00×2.20, 1.0 pitch)		325 (300/25)
TFBGA324 (15.00×15.00×1.30, 0.8 pitch)		176 (151/25)

Note：
1. Each 36Kb EMB unit integrates one hardcore FIFO controller, which can be split into independently two 18Kb EMBs or four 9Kb EMBs.
2. Each DSP contains one pre-adder, one 18*35 or 18*34 multiplier, and each multiplier can be split into two 18*18 or four 18*9 or eight 10*10 sub multipliers; 1 post-adder that supports accumulator function.
3. One 18*18 may be implemented by four 10*10, and one 35*18 may be implemented by two 18*18.
4. Each GCLK_TILE contains one PLL.
5. x32 and x16 device support.

Application Cases

Title	Document ID	Version	Release Date	File Format
HME-P3_Family_FPGA_Flyer_EN		V_1.2	2026-04-21	PDF
HME-P3 Family_FPGA_Data_Sheet_EN		V_0.3	2026-04-21	PDF