HME - PV65-Products Center

FPGA
6-input Look-up Tables High Performance FPGA Fabric		40,800 LUT6 81,600 register elements
Embedded Memory Block		112 36Kb programmable true-dual-port EMB block, totaling 4032Kb LRAM with a total capacity of 368Kb
Embedded DSPs block		104 DSP (MAC) blocks, 3518 or 208 DSP（MAC) blocks, 1818 or 416 DSP (MAC) blocks, 189 or 832 DSP（MAC）blocks, 1010
Clock Network		32 de-skew global clocks - Flexible hierarchical clock network 1 OSC 9 PLLs Dynamic clock management in system
I/O		HRIO Support the following single-ended standards: 3.3/2.5/1.8/1.5/1.2V LVTTL/LVCMOS Supports IDDR and ODDR function up to 1:4 Support hot-socket
		HPIO Support the following single-ended standards: 1.8/1.5/1.2V LVCMOS/LVTTL and 1.8/1.5/1.35/1.2V SSTL/HSTL Support the following differential standards: LVDS RX/TX, BLVDS, Sub-LVDS, SLVS - Support for on-chip termination resistors Support to IDDR and ODDR function up to 1:16 Support for MIPI D-PHY level standard Up to 1.5Gb/s per LVDS I/O Support to IDDR and ODDR function up to 1:16
MCU
ARM Cortex-M3 MCU	High performance 32-bit processor, frequency up to 200MHz Outstanding processing performance combined with fast interrupt handling Enhanced system debug with extensive breakpoint and trace capabilities Integrated sleep mode
Peripheral	8 Timers 1 Watch Dog Timer 3 I2C interfaces 3 SPI interfaces 1 QSPI interface 3 UART interfaces 1 GPIO, 32-bit 1 4-channel DMA
SERDES
4 lanes TX/RX supporting protocols up to 12.5 Gbps
Harden PCIe Gen 3 with x4 lanes
Memory
Embedded SRAM Block	2 SRAMs, 4K*32b, total 32KB
MIPI
D-PHY@4.5Gbps data rate
C-PHY@2.5Gsps data rate
Configuration
Configuration Mode	- JTAG Mode - AS Mode - PS Mode
In System Configuration
Boot	- Single-boot - Dual-boot - Multi-boot
Security
256-bit eFuse 128-bit AES encrypted data stream Protects FPGA bitstreams and MCU firmware
Package
PBGA676

Part Number		PV65EXC0	PV65EXC1	PV35EXC0	PV35EXC1	PV15EXC0	PV15EXC1
Programmable Logic Block(PLB)	Logic cells(K)	65	65	35	35	15	15
	LUT6	40,800	40,800	21,900	21,900	9,400	9,400
	Register	81,600	81,600	43,800	43,800	18,800	18,800
Embedded Memory Block (EMB)	36Kb	112	112	60	60	38	38
	18Kb	224	224	120	120	76	76
	9Kb	448	448	240	240	152	152
	Max(Kb)⁽¹⁾	4,032	4,032	4,032	4,032	4,032	4,032
Local RAM （LRAM）	Max(Kb)	368	368	200	200	123	123
DSP⁽²⁾	35b*18b⁽³⁾	104	104	56	56	35	35
	18b*18b	208	208	112	112	70	70
	18b*9b	416	416	224	224	140	140
	10b*10b	832	832	448	448	280	280
GCLK_TILE⁽⁴⁾		9	9	9	9	9	9
SERDES Channels		4	4	4	4	4	4
MIPI	C-PHY Rx	-	2	-	2	-	2
	C-PHY Tx	-	2	-	2	-	2
	D-PHY Rx	2	2	2	2	2	2
	D-PHY Tx	2	2	2	2	2	2
OSC		1	1	1	1	1	1
PVTS		4	4	4	4	4	4
MCU	Cortex-M3	1	1	1	1	1	1
	UART	3	3	3	3	3	3
	I2C	3	3	3	3	3	3
	SPI	3	3	3	3	3	3
	GPIO	64	64	64	64	64	64
	Timer	8	8	8	8	8	8
	WDG	1	1	1	1	1	1
	DMA	1	1	1	1	1	1
SRAM	4K*32b	4	4	4	4	4	4
SRAM	Total(KB)	64	64	64	64	64	64
eFuse	256b	1	1	1	1	1	1
Package (unit: mm)		Max User IO (HRIO/HPIO/DEDIO/CFGIO)
PBGA324 (27.00x27.00x2.20, 1.0 pitch)		314 (72/150/75/17)	314 (72/150/75/17)	314 (72/150/75/17)	314 (72/150/75/17)	314 (72/150/75/17)	314 (72/150/75/17)

NOTE

Each 36Kb EMB unit integrates one hardcore FIFO controller, which can be split into independently two 18Kb EMBs or four 9Kb EMBs.
Each DSP contains one pre-adder, one 18*35 or 18*34 multiplier, and each multiplier can be split into two 18*18 or four 18*9 or eight 10*10 sub multipliers; 1 post-adder that supports accumulator function.
One 18*18 may be implemented by four 10*10, and one 35*18 may be implemented by two 18*18.
Each GCLK_TILE contains one PLL.

Application Cases

Title	Document ID	Version	Release Date	File Format
HME-PV_Family_FPGA_Flyer_EN		V_1.0	2026-04-03	PDF
HME-PV_Family_FPGA_Data Sheet_EN		V_1.0	2026-04-03	PDF