• realize the perfect combination of 8051 and FPGA, flexible operation and good scalability
• using a new high-performance Tile architecture
• addition chain structure without logic resources
• integrates two 4 Lane 1.5GMIPI D-PHYs and transceiver controllers
• Wafer-level CSP package
• single-chip high-performance video bridge
• most cost-effective FPGA

FPGA

SRAM-based FPGA Fabric

-  Up to 2K 6-input Look-up Tables, 4096 DFF-based registers

-  Performance up to 200MHz

Embedded RAM Block Memory

-  8 18Kbit programmable dual-port DPRAM memory

Embedded DSPs block

-  16 18x18 DSP (MAC) blocks or 32 12x9 DSP (MAC) blocks

Clock Network

-  8 de-skew global clocks

-  1 +/-5% frequency accuracy after trimming OSC

-  1 PLLs support frequency multiplication,

frequency division, phase-shifting, de-skew

-  6 external input clocks,

-  Dynamic clock management in system

Two hardened 4-lane MIPI interfaces

-  Programmable transmit and receive D-PHY

-  1.5Gb/s one lane, total 6 Gb/s per D-PHY

-  Programmable host and peripheral MIPI

controller

I/O

-  3.3/2.5/1.8/1.5/1.2V LVTTL/LVCMOS general I/O

-  Programmable source synchronous I/O

   Emulated MIPI D-PHY, LVDS Rx, LVDS Tx, BLVDS

   Up to 1200 Mb/s per I/O

MCU

 Enhanced 8051 MCU

-  Reduced instruction cycle time (Up to 12 times in respect to standard 8051), frequency up to 80MHz

-  Compatible to 8051 instruction system

-  Support up to 8MB data/code memory extension

-  Support hardware 32/16-bit MDU

-  On-chip debugger system (OCDS)

-  8-channel DMA

Peripheral

-  3 16-bit Timers

-  1 I2C interface

-  1 SPI interface

   Master rate up to 100Mb/s @200MHz

   Slave rate up to 25Mb/s @200MHz

-  2 Full Duplex Serial Interfaces, the rate is up to 6.25Mb/s @200MHz

-  Enhanced hardware operation unit supports multiplication, division, skip and normalization.

STOP,IDLE Mode Power Management

Memory

Embedded SRAM Memory

-  8Kx32b single-port SRAM

-  2*2Kx32b single-port SRAM

-  Flexible memory configuration for FPGA or MCU

Configuration

Configuration Mode

-  JTAG Mode

-  AS Mode

-  PS Mode

JTAG Interface

-  JTAG Chip Configuration

-  JTAG 8051 Debugging

Security

Encrypted Bitstream with 256-bit AES

Protection against copying, overbuilding, cloning and tampering with both of customer's FPGA and 8051 firmware IP