中文版
The HME-Pegasus P1P060 family is a low-power, high-performance and high-density FPGA device which supports the most advanced programmable logic, IO expansion, high bandwidth memory operation and highspeed data communication. Built on a mature 40nm process technology. The Pegasus family offers a new and more efficient 6-input look up table (LUT) logic with dual-register and rich selection of built-in system-level blocks. These include 18 Kb (2 x 9 Kb) block RAMs, second generation DSP56V1 slices, DDR memory controllers and PHY, enhanced PLL, and clock management blocks, power optimized high-speed serial transceiver blocks, PCI Express® compatible endpoint blocks, advanced system-level power management modes, 1MSPS XADC, auto-detect configuration options, and enhanced IP security with AES protection.
HME-P1P060 family offers better solution for high-volume logic designs, high-speed computing designs, and high-performance demand applications.
SRAM-based FPGA Fabric
- 40nm CMOS process technology
- 36,864 6-input LUTs
- a new 6-input Lookup Table (LUT) logic
- up to 6.5G bps Serdes highspeed I/O
Hardened Memory Controller and PHY
- support 32/16-bit DDR2/3
- data rates up to 1,333 Mb/s
- gen1/2 End Point, Root Complex
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Part number |
P1P060 |
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|
Programmable Logic Block (PLB) |
Logic cells |
58,982 |
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|
LUT6 |
36,864 |
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Register (DFF-based) |
73,728 |
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嵌入式内存模块（EMB） |
LRAM |
576 Kb |
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|
18Kb EMB |
144 |
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9Kb EMB |
288 |
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Total EMB |
2,592 Kb |
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Clock & PLL |
PLL |
4 |
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Global CLock |
32 |
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DSP |
DSP Slice (DSP56V1) |
144 |
|
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18 x 18 Multiplier |
288 |
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Hard IP |
PCI Express Gen1/2 |
1 |
|
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DDR2/3 (PHY & controller) (1) |
1 |
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Transceiver |
Configurable 300M~6.5G |
4 |
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XADC(1MSPS) (2) |
2 |
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Package (unit: mm) |
Max User I/O （LVDS pair）Transceiver / DDR |
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FBGA784 (29x29x3.32, pitch 1.0) |
477 (144) / 4 / 32b |
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VFBGA324 (15x15x1.93, pitch 0.8) |
209 (64) / 0 / 16b |
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FCCSP325 (15x15x1.21, pitch 0.8) |
209 (64) / 0 / 16b |
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Notes:
(1) All the DDR pin can't be used as l/O if the DDR lP is used.
(2) The ADC can be used to monitor the internal chip temperature and voltage.
| Title | Version | Release Date | File Format |
| HME-Pegasus_P1P060 Family FPGA DataSheet | V_1.5 | 2023-01-22 | |
| HME-Pegasus_P1P060 Family_Data Sheet | V_1.7 | 2023-05-22 | |
| HME-P1 Family_User Guide_Clocking Resource | v_1.0 | 2022-09-21 | |
| HME-P1 Family_User Guide_ADC | V_1.0 | 2022-09-29 | |
| HME-P1 Family_User Guide_EMB | V_1.0 | 2020-10-25 | |
| HME-P1 Family_User Guide_FIFO | V_1.0 | 2022-10-27 | |
| HME-P1 Family_User Guide_Configuration Mode | V_1.0 | 2022-09-27 | |
| HME-P1 Family_User Guide_Hardware Design | V_1.0 | 2022-09-30 | |
| HME-P1P060_pinlist | V_3.0 | 2022-06-06 | Excel |
| HME-P1 Family User Guide LVDS | V_1.0 | 2022-10-21 |
HME - P1P060(12)