Feature
High Performance SRAM-based FPGA
High-performance, low-power consumption, 32-bit RlSC processor (ARM@ Cortex™-M3)
Performance up to 200MHz
Dual 12 bit 1MSPS ADC and other standard Peripherals
Multi-voltage, multi-standard, multi-banks I/O and packages
Richness of peripherals devices with ETH, USB, CAN, DMA controlers and DDR
8 external input clocks, 1 external crystal clock input
Embedded DSPs block
Based on efuse and SPl Flash security settings
|
Part Numberr |
M7A12N0 |
M7A12N5 | M7M12N5 | ||
|
Programmable Logic Block(PLB) |
LUT |
11520 |
11520 | 11520 | |
|
Register |
7680 |
7680 | 7680 | ||
|
Embedded Memory Block (EMB) |
4.5Kb |
144 |
144 | 144 | |
|
Max |
648Kb |
648Kb | 648Kb | ||
| SRAM | Code RAM | 128KB | 128KB | 128KB | |
| Max | 128KB | 128KB | 128KB | ||
| Data RAM | 64KB | 64KB | 64KB | ||
| Max | 64KB | 64KB | 64KB | ||
| SDRAM | - | - | 64Mb | ||
| DSP | 48 | 48 | 48 | ||
|
PLL |
4 |
4 | 4 | ||
| DLL | 4 | 4 | 4 | ||
| Crystal | 1 | 1 | 1 | ||
|
Contex-M3 |
1 |
1 | 1 | ||
|
DDRII/III Controller |
1 |
1 | 1 | ||
| USB High Speed OTG 2.0 & PHY | 1 | 1 | 1 | ||
| ETH 10/100/1000M controller | 1 | 1 | 1 | ||
| CAN 2.0 A/B | 2 | 2 | 2 | ||
| 12 bit 1MSPS ADC | 2 | 2 | 2 | ||
| UART | 3 | 3 | 3 | ||
| I2C | 2 | 2 | 2 | ||
| SPI | 2 | 2 | 2 | ||
| SPI Flash | 0 | 16Mb | 16Mb | ||
|
Max User I/O |
310 |
310 | 310 | ||
|
IPs |
Packages |
||||
| LQFP144 | FBGA256 | FBGA484 | QFN88 | ||
|
RTC |
- |
1 |
1 | - | |
|
ADC |
8ch |
2ch |
14ch | 6ch | |
|
DDR data width |
- |
16bit |
16bit | - | |
|
User I/O (LVDS pairs) |
97(27) |
156(31) |
310(75) | 59(5) | |
|
Part Number |
|||||
|
M7A12N0 |
- |
Yes |
Yes | - | |
|
M7A12N5 |
Yes | - | - | Yes | |
|
M7M12N5 |
- |
- |
- | Yes | |
| Title | Version | Release Date | File Format |
| HME-M7 Family_User Guide | V_1.7 | 2022-04-28 | |
| HME-M7_pinlist | 2023-06-13 | Excel | |
| HME-M7_Schematic Layout_User Guide | 2018-10-28 | ||
| HME-M7 Family PS Programming_Application Notes | V_1.0 | 2019-08-06 |


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