中文版
Using low power 22nm technology, HME-H3 family is built on the second-generation FPGA platform of Hercules.
HME-H3C08 FPGA family, integrates with a high-performance Cortex-M3 MCU and peripherals, hard MIPI C/D-PHY, DSI/CSI controllers, video decoder/encoder and large on-chip SRAM in a single device.
Being a high performance and low power FPGA, HME-H3 family can be used in a wide range of applications, such as high performance MCU control and processing, especially optimized for video bridging and embedded vision applications - supporting a variety of high bandwidth sensors and display interfaces.
By using configurable soft and hard lP cores, as well as the MCU of HME-H3, users are free to concentrate on their application designs for increasing the productivity.
Feature
SRAM-based FPGA Fabric
- 6-input lookup tables (LUT6), up to 4,992
- DFF-based registers, up to 9,984
Embedded RAM Block
- 8 programmable dual-port DPRAMs, 18Kb
Embedded Video Memory Block
- 16 programmable simple-dual-port memory blocks, 8KB
Embedded DSP Block
- 8 DSP (MAC) blocks, 35×18
- or 16 DSP (MAC) blocks, 18×18
- or 32 DSP (MAC) blocks, 18×9
- or 64 DSP (MAC) blocks, 10×10
Memory
Embedded SRAM Memory
- 4K×32b SRAM for MCU code memory
- 4K×32b SRAM for MCU data memory
- 4 SRAMs, 320K×32b, total 5MB
MIPI
2 hardened 4-lane MIPI PHYs
- programmable Tx D-PHY, 2.5Gb/s
- programmable Rx CD-PHY, D-PHY @2.5Gbps data rate, C-PHY @2.5Gsps symbol rate
- programmable MIPI DSI/CSI host controller
- programmable MIPI DSI/CSI peripheral controller
|
Part Number |
H3C08 |
H3D08 | H3L08 | |
|
Programmable Logic Block (PLB) |
Logic cells |
8192 |
8192 | 8192 |
|
LUT6 |
4992 | 4992 | 4992 | |
|
Register |
9984 |
9984 | 9984 | |
|
Embedded Memory Block (EMB) |
18Kb |
8 |
8 | 8 |
|
Max (Kb) |
144 |
144 | 144 | |
| Local RAM (LRAM) | 64b | 156 | 156 | 156 |
| Max (b) | 9984 | 9984 | 9984 | |
| Video Memory Block (VMB) | 8KB | 16 | 16 | 16 |
| Max (KB) | 128 | 128 | 128 | |
| DSP | 18bx18b | 16 | 16 | 16 |
|
PLL |
2 |
2 | 2 | |
|
On-chip OSC |
RC |
1 |
1 | 1 |
| LC | 1 | 1 | 1 | |
MCU |
Cortex-M3 | 1 | 1 | 1 |
| UART | 2 | 2 | 2 | |
| I2C | 2 | 2 | 2 | |
| SPI | 2 | 2 | 2 | |
| GPIO (b) | 32 | 32 | 32 | |
| Timer | 3 | 3 | 3 | |
| DMA | 1 | 1 | 1 | |
| MIPI | C-PHY Rx | 1 | - | - |
| D-PHY Rx | 1 | 1 | 1 | |
| DSI/CSI Peripheral | 1 | 1 | 1 | |
| D-PHY Tx (2.5Gbps) | 1 | 1 | 1 | |
| DSI Host | 1 | 1 | 1 | |
| SRAM | 1.25MB | 4 | 4 | 4 |
| 16KB(1) | 2 | 2 | 2 | |
| DVC | 1 | 1 | 1 | |
| EVC | 1 | 1 | - | |
| CSC | 4 | 4 | 4 | |
|
Package (unit: mm) |
Max User I/O |
|||
|
WLCSP80（4.24×4.24×0.55, 0.45 pitch） |
25 |
25 | 25 | |
|
WFBGA144（6.0×6.0×0.65, 0.50 pitch） |
44 |
- | - | |
|
Note: 1. The two 16KB SRAM are specially for MCU. |
||||
| Title | Version | Release Date | File Format |
| HME_H3_Clock&PLL_Application Notes | V_1.0 | 2023-04-26 | |
| HME-H3_PS_Programming_Application Notes | V_1.0 | 2022-05-06 | |
| HME-H3 Family FPGA_Data Sheet_EN | V_1.4 | 2023-07-25 | |
| HME-H3 Family FPGA Flyer | V_1.0 | 2023-04-06 | |
| HME-H3_pinlist | V_1.0 | Excel | |
| HME-H3 Family FPGA User Guide_EN | V_1.0 | 2023-08-23 |
HME - H3C08(7)